> set sh_continue_on_error false
> set sh_echo_on_source  true
> set sh_quiet_on_source true
> set cc_critical_as_fatal true
> set ta_report_auto_constraints 1
> 
> set_seed_rand 10
> if { ! [info exists LOGIC_TYPE] } {
 set LOGIC_TYPE "VX"
}
> if { ! [info exists LOGIC_DB] } {
  set LOGIC_DB logic_db
}
> if { ! [info exists LOGIC_DEVICE] } {
  set LOGIC_DEVICE AGRV2KL100
}
> if { ! [info exists LOGIC_MODULE] } {
  set LOGIC_MODULE top
}
> if { ! [info exists LOGIC_TOPPIN] } {
  set LOGIC_TOPPIN false
}
> if { ! [info exists LOGIC_DIR] } {
  set LOGIC_DIR .
}
> if { ! [info exists LOGIC_VX] } {
  set LOGIC_VX ${LOGIC_DESIGN}.vx
}
> if { ! [info exists LOGIC_ASF] } {
  set LOGIC_ASF ""
}
> if { ! [info exists LOGIC_PRE] } {
  set LOGIC_PRE ""
}
> if { ! [info exists LOGIC_POST] } {
  set LOGIC_POST ""
}
> if { ! [info exists VEX_FILE] } {
  set VEX_FILE ""
}
> if { ! [info exists DESIGN_ASF] } {
  set DESIGN_ASF ""
}
> if { ! [info exists DESIGN_PRE] } {
  set DESIGN_PRE ""
}
> if { ! [info exists DESIGN_POST] } {
  set DESIGN_POST ""
}
> if { ! [info exists IP_ASF] } {
  set IP_ASF ""
}
> if { ! [info exists IP_PRE] } {
  set IP_PRE ""
}
> if { ! [info exists IP_POST] } {
  set IP_POST ""
}
> if { ! [info exists LOGIC_BIN] } {
  set LOGIC_BIN ${LOGIC_DESIGN}.bin
}
> if { ! [info exists LOGIC_COMPRESS] } {
  set LOGIC_COMPRESS false
}
> if { ! [info exists IP_SDC] } {
  set IP_SDC ""
}
> 
> set db_io_name_priority $LOGIC_TOPPIN
> set ip_pll_vco_lowpower true
> 
> cd $LOGIC_DIR
> 
> if { $LOGIC_COMPRESS } {
  set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "ON"
} else {
  set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "OFF"
}
> 
> set logic_hx ${LOGIC_DESIGN}.hx
> set hx_fp [open $logic_hx r]
> set hsi_freq 0
> set hse_freq 0
> while { [gets $hx_fp line] >= 0 } {
  set words [split $line]
  if { [lindex $words 0] == "#define" } {
    if { [lindex $words 1] == "BOARD_HSI_FREQUENCY" } {
      set hsi_freq [lindex $words 2]
    }
    if { [lindex $words 1] == "BOARD_HSE_FREQUENCY" } {
      set hse_freq [lindex $words 2]
    }
    if { [lindex $words 1] == "BOARD_PLL_CLKIN" } {
      set BOARD_PLL_CLKIN [lindex $words 2]
    }
    if { [lindex $words 1] == "USB0_MODE" } {
      set USB0_MODE [lindex $words 2]
    }
  }
}
> close $hx_fp
> 
> alta::set_verbose_cmd false
> set ::alta_work $LOGIC_DB
> 
> if { "$LOGIC_PRE" != "" } {
  alta::tcl_print "Processing $LOGIC_PRE ...\n"
  source "$LOGIC_PRE"
}
> if { "$IP_PRE" != "" } {
  alta::tcl_print "Processing $IP_PRE ...\n"
  source "$IP_PRE"
}
> if { "$DESIGN_PRE" != "" } {
  alta::tcl_print "Processing $DESIGN_PRE ...\n"
  source "$DESIGN_PRE"
}
> eval "load_architect -type $LOGIC_DEVICE"
Total IO  : 150
Total Pin : 128/17
Top array is built.
Loading architect libraries...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 50MB (50MB)
Loading route table...

## CPU time: 0:0:0, REAL time: 0:0:3
## Memory Usage: 314MB (314MB)
> 
> set sdc_file $::alta_work/alta.sdc
> set sdc_fp [open $sdc_file w]
> if { "$IP_SDC" != "" } {
  if { $hsi_freq != 0 } {
    puts $sdc_fp "set ::HSI_PERIOD [expr 1000000000.0/$hsi_freq]"
  }
  if { $hse_freq != 0 } {
    puts $sdc_fp "set ::HSE_PERIOD [expr 1000000000.0/$hse_freq]"
  }
  set ip_sdc_fp [open $IP_SDC r]
  while { [gets $ip_sdc_fp line] >= 0 } {
    puts $sdc_fp $line
  }
  close $ip_sdc_fp
} else {
  puts $sdc_fp {derive_pll_clocks -create_base_clocks}
}
> close $sdc_fp
> 
> if { "$LOGIC_TYPE" == "VX" } {
  read_design -top $LOGIC_MODULE -ve $VEX_FILE -qsf "" $LOGIC_VX -hierachy 1
  alta::tcl_print "Processing $sdc_file ...\n"
  read_sdc "$sdc_file"
} else {
  read_design_and_pack -top $LOGIC_MODULE -type vqm -sdc "$sdc_file" -gclk_level 2 $LOGIC_VX
}
Preparing design...

## CPU time: 0:0:0, REAL time: 0:0:1
## Memory Usage: 333MB (333MB)
Pseudo pack design...

Using location file example_board.vex
Info: BBOX gclksw_inst is fixed to location (22,4,0).
Info: Identified PLL output clock PLL_CLKOUT[0].
Info: Identified PLL output clock PLL_CLKOUT[1].
Info: Identified PLL output clock PLL_CLKOUT[2].
Info: Identified PLL output clock PLL_CLKOUT[3].
Info: Identified PLL output clock PLL_CLKOUT[4].
Packing Statistics
 Total      Logics :  0/2112 (  0%)
 Total        LUTs :  0/2112 (  0%)
 Total   Registers :  0/2112 (  0%)
 Total  Block Rams :  0/   4 (  0%)
 Total        PLLs :  1/   1 (100%)
 Total        Pins : 10/ 128 (  7%)
 Global    Signals :  2/   5 ( 40%)
    bus_clk (from: bus_clk_gclkgen)
    sys_gck (from:        sys_gck0)
 Total Lonely   Datain   : 0
 Total Lonely   Register : 0
 Total LUT-FF   Pairs    : 0
 Total Register Packings : 0
 Registers with synchronous    reset : 0
 Registers with asynchronous   reset : 0
 Registers with sync and async reset : 0
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 333MB (333MB)
Filter verilog...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 333MB (333MB)
Reading DB design...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 333MB (333MB)
Processing design...

> set_instance_assignment -extension -name FIXED_COORD -to gclksw_inst {22 4}
> set_location_assignment -to GPIO4_1 PIN_26
> set_location_assignment -to GPIO4_2 PIN_27
> set_location_assignment -to GPIO4_3 PIN_28
> set_location_assignment -to GPIO4_4 PIN_29
> set_location_assignment -to GPIO6_2 PIN_25
> set_location_assignment -to PIN_HSE PIN_HSE
> set_location_assignment -to PIN_HSI PIN_HSI
> set_location_assignment -to PIN_OSC PIN_OSC
> set_location_assignment -to UART0_UARTRXD PIN_31
> set_location_assignment -to UART0_UARTTXD PIN_30
Info: Found GCLK net bus_clk (0).
Info: Found GCLK net sys_gck (0).
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 334MB (334MB)
Processing logic_db/alta.sdc ...
derive_pll_clocks -create_base_clocks
Info: Auto constraint PLL: create_clock -name PIN_HSE -period 50.000 PIN_HSE.
Info: Auto constraint PLL: create_generated_clock -name pll_inst|clkout0 -multiply_by 25 -add -source PIN_HSE -master_clock PIN_HSE pll_inst|clkout0.
Info: Auto constraint PLL: create_generated_clock -name pll_inst|clkout3 -divide_by 2 -multiply_by 25 -add -source PIN_HSE -master_clock PIN_HSE pll_inst|clkout3.
> 
> set_mode -skew basic -effort high -fitting auto -fitter full
>  set pl_criticality_wratio  "2.50 2.50 2.50 1.00"
> #set pl_max_iter_eco        "10 20 300 40 3  100 100 1"
> ##et pl_eco_slack_crit      "99999. 1.00  0.10 7 0.03 30 0.01 150"
> 
> ##et pl_priority_compare  "2 2 2 3"
> #set pl_priority_result   "2 1 1 0"
> #set pl_priority_pass     "2 1 1 0"
> #set pl_swap_cost_margin       "200.0  0.0  200.0  0.0  200.0  0.0   0.00  0.0"
>  set pl_swap_wirelength_margin "200.0  0.0  200.0  0.0  200.0  0.0   020.0 -0.3  2000. 1.50"
>  set pl_swap_congestion_margin "100.0  0.0  100.0  0.0  100.0  0.0   010.0 -0.3  1000. 1.25"
> #set pl_criticality_beta "1.0 3.0 1.0  1.0 3.0 1.0  1.0 3.0 1.0  99999 3.0 3.0"
> #set pl_oci_iter "1 1 100 1"
> 
>  set rt_retiming_idx         5
>  set rt_converge_accelerator "2 1 0 3"
> #set rt_pres_cost_ratio      "1.00 1.50  2.00 2.50"
>  set rt_dly_ratio            "0.55 0.35 0.30  0.50 0.50 0.30"
>  set rt_reroute_max_iter     "6  5 6  7 9  12"
>  set rt_reroute_start_iter   "0  1 2  2 4  0 "
>  set rt_quick_converge_ratio 0.25
>  set pl_reuse_existing_placement false
>  set pl_fix_bram_cells 0
>  set pl_fix_mult_cells 0
>  set pl_neighbor_swap_range "3  6  6  3 "
>  set pl_pass_result "1 1 1 1"
>  set pl_max_pass    "1 1 1 1 1"
>  set pl_max_iter       10
>  set pl_max_iter_part  20
>  set pl_max_iter_final 20
>  set pl_max_iter_legal 10
>  set pl_max_iter_touch 00
> #set pl_neighbor_swap_range "2  6  6  3 "
> #set pl_spread_swap_max_iter "3 5  5 4"
> #set pl_use_initial_place_once 0
>  set rt_min_converge "5"
>  set rt_optimize_max "3"
>  set pl_useful_skew_level -1
>  set rt_useful_skew_level 0
>  set rt_useful_skew_bram         true
>  set rt_useful_skew_io           false
>  set rt_useful_skew_io_ireg      false
>  set rt_useful_skew_io_oreg      false
>  set rt_useful_skew_output_io    false
>  set rt_useful_skew_input_io     false
>  set rt_useful_skew_unconstraint "false false"
>  set rt_useful_skew_max                "0 100"
>  set rt_skew_crit_minmax               "0.00 1.00"
> #set rt_useful_skew_setup_slac_margin  "1.00 1.00  1.00 1.00  1.00 0.10 0.50 0.10 0.70 0.10  1.00"
> #set rt_useful_skew_hold_slack_margin  "0.10 0.10  0.30 0.30  0.30 0.30"
> #set rt_useful_skew_hold_slack_ratio   "0.05 0.05  0.10 0.10  0.10 0.10"
> 
> if { "$LOGIC_ASF" != "" } {
  alta::tcl_print "Processing $LOGIC_ASF ...\n"
  source "$LOGIC_ASF"
}
Processing C:/Users/94336/.platformio/platforms/AgRV/boards/agrv2k_303/board.asf ...
> if { [info exists BOARD_PLL_CLKIN] } {
  if { $BOARD_PLL_CLKIN == "PIN_OSC" } {
    set_config -loc 18 0 0 CFG_RCOSC_EN 1'b1
  }
}
> if { [info exists USB0_MODE] } {
  alta::tcl_info "USB0_MODE = $USB0_MODE"
  set_config -loc 0 1 3 CFG_PULLUP_ENB 1'b0
  set_config -loc 0 1 3 CFG_PULLDN_ENB 1'b0
}
> if { "$IP_ASF" != "" } {
  alta::tcl_print "Processing $IP_ASF ...\n"
  source "$IP_ASF"
}
> if { "$DESIGN_ASF" != "" } {
  alta::tcl_print "Processing $DESIGN_ASF ...\n"
  source "$DESIGN_ASF"
}
Processing D:/AGM_WORK/AgRV_pio/platforms/AgRV/examples/example_demo_48pin/./example_board.asf ...
> puts "************ DESIGN ASF ************"
************ DESIGN ASF ************

> 
> # Enable PIN_23 (WKUP pin) to wake up device from standby. This function is not available on other pins.
> set_config -pin PIN_23 CFG_WKUP_EN 1'b1
Error: Unrecognized IO pin PIN_23.
> # Use falling edge of the WKUP pin. By default rising edge is used.
> set_config -pin PIN_23 CFG_WKUP_INV 1'b1
Error: Unrecognized IO pin PIN_23.
> 
> place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io
> 
> set rt_max_iter "150 1 750 50  2 2"
> alta::set_verbose_cmd true
> place_and_route_design -quiet -retry 3
Warn: Auto constraint INTERNAL: create_clock -name Internal_generated_clock_top|PIN_HSI -period 1000.000 PIN_HSI.
Placement Statistics
 Total  Logic    Counts  : 0/2112 (0.0%)
 Total  Logic    Tiles   : 0/132 (0.0%)
 Total  Valid    Nets    : 24 (22+2)
 Total  Valid    Fanouts : 49 (45+4)
 Total  Tile     Fanouts : 21
 Tile   Zip      Fanins  : 0 (0:0)
 Tile   Zip      Fanouts : 0 (0:0)
 Total  Ignored  Nets    : 278
 Total  Valid    Blocks  : 6 (0/4)
 Total  Ignored  Blocks  : 0
 Total  Zip Complexities : 5/20 1.52/7.61
 Avg    Zip   Bottleneck : 0.00 0.00
 Avg    Net   Bottleneck : 0.00 0.00
Total wire cost after placement: 0.0:0.0%(0.0:0.0%) 35.893(0)+217(0)+0 221.104(33.019)+223.5
Route Design Statistics
 Total Routing Nets : 24
 Fanout     Average : 1.04 (1..2)
 Max   Fanout  Net  : sys_clk
 Logic       Slices : 0/2112 (0.0%)

Routing...
 Budget Useful Skew...
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 1/1, route#: 24, violation# : 8, overflow# : 8, conflict# : 12, node#: 133
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 2/2, route#: 24, violation# : 5, overflow# : 5, conflict# : 8, node#: 138
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 3/3, route#: 24, violation# : 1, overflow# : 1, conflict# : 2, node#: 155
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 4/4, route#: 24, violation# : 0, overflow# : 0, conflict# : 0, node#: 157
Optimizing...
...

Done


*** Post Routing Timing Report ***

=== User constraints ===
=== Auto constraints ===
Coverage report
  User constraints covered 4 connections out of 26 total, coverage: 15.4%
  Auto constraints covered 5 connections out of 26 total, coverage: 19.2%
*** End Timing Report ***



> alta::set_verbose_cmd false
> 
> report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
> report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz
> report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
> report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz
> 
> set ta_report_auto_constraints 0
> report_timing -fmax -file $::alta_work/fmax.rpt
> report_timing -xfer -file $::alta_work/xfer.rpt
> set ta_report_auto_constraints 1
> 
> set ta_dump_uncovered 1
> report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
Warn: User constraints coverage is too low at 15.4%.
> unset ta_dump_uncovered
> 
> set logic_routed ${LOGIC_DESIGN}_routed.v
> write_routed_design $logic_routed
> 
> bitgen normal -bin $LOGIC_BIN
> alta::bin_to_asc $LOGIC_BIN [file rootname $LOGIC_BIN].inc
> 
> if { "$LOGIC_POST" != "" } {
  alta::tcl_print "Processing $LOGIC_POST ...\n"
  source "$LOGIC_POST"
}
> if { "$IP_POST" != "" } {
  alta::tcl_print "Processing $IP_POST ...\n"
  source "$IP_POST"
}
> if { "$DESIGN_POST" != "" } {
  alta::tcl_print "Processing $DESIGN_POST ...\n"
  source "$DESIGN_POST"
}
> 
> exit

Total 0 fatals, 2 errors, 2 warnings, 11 infos.
